1. Field of the Invention
The present invention relates generally to integrated circuits, and more specifically to a structure and method for fabricating integrated circuits.
2. Description of the Prior Art
Self-aligned twin well formation is a process used during conventional CMOS integrated circuit fabrication. In this process, a barrier layer is used as a mask during implantation of impurities of one conductivity type into a semiconductor substrate. Thermal oxide is formed in the exposed regions of the semiconductor substrate and the barrier layer is then removed. The thermal oxide is used as a mask during implantation of impurities of a second conductivity type. The thermal oxide is removed, and the integrated circuit heated to form the twin wells within the substrate.
As known in the art, formation of the thermal oxide also results in oxidation of a portion of the semiconductor substrate. Consequently, the surface of the semiconductor substrate loses its planarity when the thermal oxide is removed. The upper surface of one well is lower than the upper surface of the other well.
This loss of planarity is a problem during subsequent processing steps, such as the formation of gate electrodes on the surface of the twin wells. Because the surfaces of the twin wells are not coplanar, mask focusing problems occur during patterning of the gate electrodes. This causes the critical dimensions of the gate electrodes to differ. As known in the art, these focusing problems cause numerous problems with the manufactured integrated circuits.
Therefore, it would be desirable to provide a method for forming twin wells in a semiconductor substrate which will have coplanar surfaces. It is also desirable that such a method not significantly increase the complexity of the fabrication process.
According to the present invention, a structure and method is provided for fabricating an integrated circuit having an N-type well and a P-type well, with the upper surfaces of the N-type well and the P-type well coplanar. An insulating layer is formed over the integrated circuit. A first masking layer is formed over the insulating layer to define locations of a first well to be formed. An impurity of a first conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a first region. The first masking layer is removed, and a second masking layer is formed over the insulating layer to define locations of a second well to be formed. An impurity of a second conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a second region. The second masking layer is then removed. The integrated circuit is thermally heated to drive the first and second regions deeper into the substrate to form the first and second wells. If desired, sets of alignment keys may be formed in a semiconductor wafer by first forming a layer of insulating material over a semiconductor wafer, followed by forming a layer of masking material to define the locations of the sets of alignment keys and anisotropically etching into the semiconductor wafer to form the sets of alignment keys. The sets of alignment keys may be formed in a portion of the semiconductor wafer that is not part of a substrate for any particular integrated circuit.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIG. 1 is a sectional view of an integrated circuit illustrating a prior art structure and method for fabricating integrated circuits; and
FIGS. 2-7 are sectional views of an integrated circuit illustrating a preferred structure and method for fabricating integrated circuits according to the present invention.